Invited Talks



Professor Krishna Saraswat
Stanford University

Real Limits to Nanoelectronics - Interconnects and Contacts

Speaker Biography

Prof. Krishna Saraswat is Rickey/Nielsen Professor in the School of Engineering, Stanford University, California, USA. He received M.S. and Ph.D. degrees in Electrical Engineering in 1969 and 1974 respectively from Stanford University. After graduating he joined Stanford University as a Research Associate in 1975 and later became a Professor of Electrical Engineering in 1983. He has also advised several academic and government organizations all over the world.

In the first 15 years upon graduation from Stanford, he worked on silicon semiconductor fabrication technology. He pioneered the technologies for aluminum/titanium layered interconnects, CVD of tungsten and tungsten silicide MOS gates. During the late 80’s he became interested in the economics and technology of single wafer manufacturing. He developed equipment and simulators for single wafer thermal processing, deposition and etching and technology for the in-situ measurements and real-time control. Jointly with Texas Instruments a microfactory for single wafer manufacturing was demonstrated in 1993. Since the mid 90’s he has been working on new materials, devices and interconnects for scaling MOS technology to sub-10 nm regime. He has pioneered several new concepts of 3-D ICs with multiple layers of heterogeneous devices. His group demonstrated the first high performance germanium CMOS and III-V antimonide CMOS with metal gate and high-k dielectrics. His current research is on new device structures to continue scaling MOS transistors and semiconductor memories to nanometer regime, 3-dimentional ICs with multiple layers of heterogeneous devices, optical interconnections, and high efficiency and low cost solar cells. He has authored or co-authored 15 patents and over 785 technical papers, of which 10 have received Best Paper Award.

Dr. Saraswat is an IEEE Life Fellow. He received the Thomas Callinan Award in 2000, the 2004 IEEE Andrew Grove Award, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007, BITS Pilani Distinguished Alumnus Awards in 2012 and the Semiconductor Industry Association (SIA) Researcher of the Year Award in 2012. He is listed by ISI as one of the Highly Cited Authors in his field.


Silicon bulk CMOS dominated the microelectronics industry in the past with the rapid scaling of device dimensions. However, future Si technology is reaching practical and fundamental limits. To go beyond these limits FinFETs have been introduced and novel device structures like surround gate FETs, Tunnel-FETs, etc. and potentially higher performance material like Ge, III-Vs, carbon nanotubes and 2D materials are being aggressively studied. However, as device scaling continues, parasitic source resistance largely dominated by contact resistance, is beginning to limit the device performance. Historically the method to reduce ρc is by increasing doping density thereby thinning the barrier, thus allowing more tunneling current. This method works well for n-Si and p-Ge which can be doped heavily. However, it is not very practical for n-Ge, p-Si, many III-Vs and 2D materials because of inability to dope them heavily. In this talk we will explore other alternatives to reduce contact resistance, such as, metastable doping, Fermi level de-pinning and band engineered heterostructures.

While novel structures and materials have enhanced the transistor performance, the opposite is true for the interconnects that link these transistors. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects, including excessive power dissipation, insufficient communication bandwidth, and signal latency for both off-chip and on- chip applications. Many of these obstacles stem from the physical limitations of copper/low-k electrical wires, namely the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in copper and the dielectric capacitance. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. This talk will address effects of scaling on the performance of Cu/low-k interconnects, alternate interconnect schemes: carbon nanotubes (CNT), graphene, optical interconnect, three-dimensional (3-D) integration and heterogeneous integration of these technologies on the silicon platform.


Dr. Meikei Ieong
Hong Kong Applied Science and Technology Research Institute, ASTRI

Emerging Applications with More-than-More Technologies

Speaker Biography

Dr. Ieong is currently Chief Technology Officer at Hong Kong Applied Science and Technology Research Institute (ASTRI). Prior to this, He has held various engineer and leadership positions in Taiwan Semiconductor Manufacturing Company (TSMC) and IBM Research. He holds a PhD degree in Electrical and Computer Engineering from University of Massachusetts, Amherst and an MBA degree from the MIT Sloan Fellows Program at MIT School of Management.

Dr. Ieong was General Chairman of the IEEE International Electron Devices Meeting (IEDM). He has served as an editor for the IEEE Transaction on Electron Devices since 2010 and as chair of the IEEE EDS Education Award committee since 2013. He has Published more than one hundred papers in referred journals and conference proceedings and more than eighty patents. He is an IEEE Fellow in recognition of his leadership and contributions to Complementary Metal-Oxide-Semiconductor (CMOS) Device Technology. Currently, he is an elected Board of Governor of IEEE EDS.


Moore’s Law has been by an large the key enabler for the growth of electronic industry. But fundamental limits and economic law has slowed down the adoption of advanced technology. More-than-Moore technologies add values to devices by incorporating functionalities that do not necessarily scale according to Moore's Law. In this talk, I will review several emerging applications ranging from sensor, computing, energy/power and Internet-of-Things. These applications have been and will be the main driver for the increasing demand for the More-than-Moore technologies.