Professor Shinichi Takagi
University of Tokyo
Course-1: Advanced devices and materials for future CMOS-based IC Technologies
- High mobility MOSFET Technology
- III-V semiconductors
Shinichi Takagi received the B.S., M.S. and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 1982, 1984 and 1987, respectively. His Ph.D. thesis involved the study on the surface carrier transport in MISFETs based on III-V semiconductors.
He joined the Toshiba Research and Development Center, Kawasaki, Japan, in 1987, engaged in the research on the device physics of Si MOSFETs, including the carrier transport in the inversion layer, the impact ionization phenomena, the hot carrier degradation and the electric properties of Si/SiO2 interface. From 1993 to 1995, he was a Visiting Scholar at Stanford University, Stanford, CA, where he studied the Si/SiGe hetero-structure devices. Since returning to the ULSI Research Laboratories, he was also engaged in the physics and technology of the reliability of SiO2, ferroelectric devices and strained-Si MOS devices. He worked for the MIRAI Project as the leader of Ultra-High Performance New Transistor Structures Theme from 2001 to 2007. In October 2003, he moved to the University of Tokyo, as a professor in the department of Electrical Engineering and Information Systems, School of Engineering. His recent interests include the science and the technologies of advanced CMOS devices using new channel materials such as strained-Si, Ge and III-Vs. He has published more than 572 papers in Journal and conferences.
Dr. Takagi is a Japan Society of Applied Physics Fellow, member of the IEEE Electron Device Society and the Japan Society of Applied Physics. He has served on the technical program committee of several premier conferences including IEDM, Symposium on VLSI Technology, IRPS, SSD< ISSCC Among numerous awards, he received Andrew S. Grove award, (2013) Purple Ribbon Medal (2017, Japan), IEEE Paul Rappaport Award (2013), EDS George E. Smith Award (2003), etc. and several best papers in IEEE conferences.
Eric Y. Wang
Intel, Hillsboro Oregon, USA
Course-2: Embedded Memory Design in CMOS Technology
- CMOS Technology Scaling
- Embedded Memory Technologies
- Scaling Trend and Applications
- Challenges, Circuit Techniques and Reliability
- Technology, applications and status
Dr. Yih Wang received his B.S. degree in Electrical Engineering from National Tsing Hua University, Hsinchu, Taiwan, and the M.S. and Ph.D. degrees in electrical and computer engineering from University of Florida in U.S.A. He joined Intel Portland Technology Development in 2001 and now is a senior principal engineer in logic technology development group at Intel, responsible for the development of low-power and high-speed embedded memory technologies. He has worked on designs of standard-cell library, low-power and high-speed embedded memories from 90-nm to 14-nm CMOS technologies. He has received three Intel Achievement Awards for his contributions on embedded memory technology development. He has been one of the key speakers in the short course of 2016 VLSI symposium. He has authored and co-authored more than 36 journal and conference publications and has more than 40 issued and pending U.S. patents. He is a senior member of the IEEE.